Flag assertion still running at end of simulation as an error

SystemVerilog
8

In reply to snixon:

This was flagged as an assertion error after executing $finish:

module top;
   bit clk,req,gnt;
   property p;
      @(posedge clk) req |-> strong(##[0:$] gnt);
   endproperty
   assert property (p);
   always #1 clk = ! clk;
   initial begin
      @(negedge clk)
      @(negedge clk) req  = 1;
      @(negedge clk) req  = 0;
     @(negedge clk) //gnt = 1;
      @(negedge clk)
      $finish;
   end
endmodule