First_match Error

SystemVerilog
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5

In reply to ben@SystemVerilog.us:

Hi Ben,
As I stated earlier, the requirement is, “**the first bit of the data sample must be at the rising edge of the clock”
**
Meaning, Assertion should ONLY check first bit of the data sample. In this case

  • there are 4 data lines which start transferring data when clock is enabled
  • The Assertion should check if and only if FIRST bit of data sample (d1 or d2 or d3 or d4) is on rising edge of the clock. If YES, Assertion must stop checking further and assert PASS, if not it should stop checking and assert an ERROR.
  • The Assertion ONLY meant to check first bit not the entire sequence (that is why I used first_match earlier)

Thanks for your patience and inputs.