First_match Error

SystemVerilog
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4

In reply to bhataksh:
It sounds like your assertion is NOT expressing your requirements.
You say that the assertion must stop after it finds first bit of data on the rising edge. But the following assertion states the following:

 // At every clock edge of dclk_p, if either of the following bits ==1, then dclk_p==0. 
// Those bits include d1_p, d2_p, d3_p, d4_p
//An assertion of this property is tested at every clock edge of dclk_p, 
// and last ONLY ONE cycle. 
property p_data_first_bit(logic data);
	@(dclk_p)  disable iff (!reset)
		(d1_p || d2_p || d3_p || d4_p) |-> dclk_p==0); 
endproperty

When you say assertion must stop after it finds first bit of data on the rising edge
Exactly, what do you mean by that? Anyone of those bits at any cycle ==1, then you have a rising edge? That’s what you have expressed.

you seem to imply a sequence that lasts more than ONE cycle.
I suggest that you express your requirements in English. If the following are your requirements:

  • There is a sequence of bits that are active over several cycles.
  • These bits are checked at the clock edges of dclk_p
  • If d1_p is followed some n cycles later by d2_p, and then some n cycles later by d3_p, some n cycles later by d4_p, then that last d4_b mys occur at the rising edge of that clock.
    Notice that we are now talking about a sequence that lasts more than one once.
  • This sequence is started at every occurrence of d1_p==1

In that case, you can do something like:

property p_data_first_bit(logic data);
  @(dclk_p)  disable iff (!reset)
  (d1_p[->1] ##1 d2_p [->1] ##1 d3_p [->1] ##1 d4_p[->1]) |-> dclk_p==0); 
endproperty
// NO first_match() is needed with the goto operator

Again, state your requirements in ENGLISH first!!!
What your first wrote was about a sequence of one cycle, and at every clocking event it either matches or does not match; thus the first_match() is totally meaningless.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us