In reply to ben@SystemVerilog.us:
In reply to bhataksh:
[list=1]
[*]
property p_data_first_bit(logic data);
disable iff (!reset)
(d1_p || d2_p || d3_p || d4_p) |-> dclk_p==0);
endproperty
Hi Ben,
Thanks for your Feedback. It truly helps!!
But, the Assertion msut stop after it finds first bit of data on the rising edge. But it keeps on checking and asserts an error when condition is not met.
I tried :
property p_data_first_bit(logic data);
disable iff (!reset)
(d1_p || d2_p || d3_p || d4_p) |-> dclk_p==0);
endproperty
as well as:
property p_data_first_bit(logic data);
disable iff (!reset)
first_match (d1_p || d2_p || d3_p || d4_p) |-> dclk_p==0);
endproperty
Both fail at 6th clock cycle. Ideally it should have stopped at 1st clock cycle when condition is satisfied !!
Please comment.