In reply to bhataksh:
I have implemented an Assertion which checks “if the first bit of the data sample is at the rising edge of the clock”
//AP_LVDS_DATA_FIRST_BIT
sequence s_data_sequence(data);
(##[0:$] (data), $display($time,“FIRST MATCH DATA”) );
endsequence
property p_data_first_bit(logic data);
disable iff (!reset)
first_match(s_data_sequence(d1_p || d2_p || d3_p || d4_p)) |-> $rose(dclk_p);
endproperty
AP_DATA_FIRST_BIT: assert property(@(dclk_p) (p_data_first_bit(d1_p || d2_p || d3_p || d4_p)))
else uvm_pkg::uvm_report_error(“AP_DATA_FIRST_BIT”,“First bit of data sample is not on rising edge of the clock”);
Error: Instead of checking only the first match, Assertion checks whole data sequence and emits an error.
Anything wrong in the sequence written?
- I don’t believe that you are using the $rose correctly. Specifically, $rose returns true when the sampled value of a Boolean signal argument transition is true at the current cycle (i.e., least significant bit of the expression==1’b1) and FALSE in the previous cycle (i.e., was 0, X, or Z), with respect to the clock of its context, otherwise it returns FALSE.
Thus, for
ap_rose: assert property(@(clk) 1|-> $rose(clk));
@ the rising edge of clk the sampled value of **rose(clk)** is 0 since the sampled value of clk in the PREPONED region is 0 and the previous sampled value of clk ==1.
2. **first_match**(##[0:](expression) |-> some_sequence
This is really the SAME thing as
(expression) |-> some_sequence
This is because at every event, if the expression==0, the assertion is vacuous. All that the first_match() does is just add more overhead on the simulator.
3. This is what I think you need.
property p_data_first_bit(logic data);
disable iff (!reset)
(d1_p || d2_p || d3_p || d4_p) |-> dclk_p==0);
endproperty
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
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