In reply to ben@SystemVerilog.us:
Yes you got the requirments correct.just one addition ACK should come before timeout or even present before the state ABS
But I wanted two write 2 assertions.
1.FSM is stays in the same state if ACK is not there before timeout.
2.FSM moves to next state once either ACK is present or if ACK is not present, it should move to next state after timeout.(is it possible to write in same assertion)