In reply to Timus:
/* The requirements are not clear. After rereading a few times, I think thta this is what you mean:
You have these objects:
typedef enum {ABS, BBS, XYZ} st_e;
st_e state;
bit clk, ack;
1) Upon a rose of state into ABS, state remains in that state until one of 2 conditions occur:
a) ack == 1
b) a timeout of 100 clock cycles
If condition "a" or "b" occurs, state transitions to BBS
*/
module m;
typedef enum {ABS, BBS, XYZ} st_e;
st_e state;
bit clk, ack;
// Conditions for state to go into BBS with the ack
ap_ABS2BBS: assert property(@ (posedge clk)
first_match($rose(state==ABS) ##1 state==ABS[*1:99] ##0 ack) |-> state==BBS);
// Conditions for state to go into BBS without the ack
ap_ABS_till_BBS: assert property(@ (posedge clk)
$rose(state==ABS) |-> ##1 state==ABS[*1:99] ##0 state==BBS);
endmodule
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
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