File based testbench

SystemVerilog
,
1

i am not getting this code can any one solve this


module tb;
  reg[3:0] a,b;
  wire[4:0] c;
  
  and_4bit dut(.a(a),.b(b),.c(c));
  
  integer test_file;
  
  initial begin
    test_file = $fopen("test_data.txt","r");
    if(test_file == 0) begin
      $fatal("\n error : could not open test_data.txt");
    end
  end
  
  integer line_num = 0;
  integer errors = 0;
  initial begin
    while(!$feof(test_file))begin
      line_num++;
      $fscanf(test_file, "%b,%b,%b" ,a,b,c);
      #1;
      if(c !== a&b) begin
        $display("\n error in line %d : expected c=%b, but got c=%b",line_num,a&b,c);
        errors++;
      end
    end
    if(errors == 0)begin
      $display("\n all tests passed!");
    end
    else begin
      $display("\n %d errors found in %d tests",errors,line_num);
    end
  end
  
  initial begin
    $fclose(test_file);
  end
  initial begin
    $fopen("test_data.txt", "w");
    $fopen("test_data.txt", "0000,0000,00000");
    $fopen("test_data.txt", "0001,0001,00001");
    $fopen("test_data.txt", "1100,0011,00000");
    $fopen("test_data.txt", "1010,0101,00000");
    $fclose("test_data.txt");
  end
endmodule
2

In reply to mahesh ardhanki:

What does ‘not getting this code’ mean? Do you have a specific question or issue?