Fifo full and empty signal for different read and write bit width

SystemVerilog
1

Help with a Fifo question ?

Construct a memory model that has different write and read side requirements
Ie write side is 32 bits, read side is 20 bits. Mem depth is 512 bytes.
How to generate full, empty conditions etc

Is the full and empty conditions same as the Memory having both read and write side 32 bits ?

Thanks,
JeffD

2

In reply to dvuvmsv:

Is the full and empty conditions same as the Memory having both read and write side 32 bits ?

Why would it be different? Your mm is 512 x 32.
You write 32 bits, read 20 bits and the other 12 are junked.

How to generate full, empty conditions etc

From my SVA book:


..
logic push; // push data into the fifo
  logic pop;  // pop data from the fifo
  logic almost_full;  // fifo is at 3/4 maximum level
  logic almost_empty;  // fifo is at 1/4 maximum level
  logic full;  // fifo is at maximum level
  logic empty; // fifo is at the zero level (no data)
  logic error; // fifo push or pop error   
  word_t data_in;
  word_t data_out;

  // local variables for verification purpose
  logic [BIT_DEPTH-1 : 0] wr_ptr = 0;
  logic [BIT_DEPTH-1 : 0] rd_ptr = 0;

  logic fifo_is_full;
  logic fifo_is_empty;
  logic fifo_is_almost_full;
  logic fifo_is_almost_empty;
...
always @ (posedge clk)
  begin : status_flag
    fifo_is_empty = (wr_ptr == rd_ptr);
    fifo_is_full = (wr_ptr - rd_ptr) == FULL; // FULL = 16; 
    fifo_is_almost_full = (wr_ptr - rd_ptr) >= ALMOST_FULL;
    fifo_is_almost_empty = (wr_ptr - rd_ptr) <= ALMOST_EMPTY;
..
task push_task (word_t data);
     begin
       $display ("%0t %m Push data %0h ", $time, data);
	   data_in <= data;
	   push <= 1'b1;
	   pop  <= 1'b0;
       	   wr_ptr++;
	   ##1;
      end
    endtask : push_task 

    task pop_task;
      begin
        data_in <= 'X; // unsized Xs 
        push <= 1'b0;
        pop  <= 1'b1;
        rd_ptr++;
        ##1;
       end
    endtask : pop_task

  end : status_flag

Ben Cohen
Ben@systemverilog.us
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