Hi,
I was wondering if anyone else encounter the situation were the register model mirror value isn’t updating when using uvm_predictor?
MY code:
//predictor declaration
uvm_reg_predictor#(svt_axi_transaction) predictor;
//build phase
predictor= uvm_reg_predictor#(svt_axi_transaction)::type_id::create("predictor", this);
//connect phase
predictor.map = cfg.reg_model.fpga_top.default_map;
predictor.adapter= adapter;
axi_system_env.master[0].monitor.item_observed_port.connect(predictor.bus_in);
Regards
Eran Rashkes