Few questions on Event Control

SystemVerilog
,
1

Hi All,

I was going through LRM while trying to understand the working of following code

  bit a , b ;
  
  logic c;
  
  always@(a+b)
    $display("T:%0t a+b is %0d",$time,a+b);
  
  always@(c)
    $display("T:%0t c is %0d",$time,c);
  
  always@(edge c)
    $display("T:%0t @(edge c) triggered with c == %0d",$time,c);
  
  initial begin
    #10; a = 1 ; b = 1;    
  end
    
  initial begin
    #5; c = 1'bZ;    
  end

LRM 9.4.2 Event Control says

More precisely, an edge event can be described as:

— An edge shall be detected whenever negedge or posedge is detected.

A non-edge implicit event shall be detected on any change in the value of the expression. However, an edge event shall be detected only on the LSB of the expression. A change of value in any operand of the expression without a change in the result of the expression shall not be detected as an event

I observe that always@(a+b) doesn’t trigger (on 3 eda tools) as the result of a+b (calculated using default precision of 1-bit) is 0 which is same as initial sum of default value of a & b

(Q1) I am not clear why always@(c) unblocks at T:5 units while always@(edge c) doesn’t.

I was under the impression that @(sig) is same as @(edge sig)

I believe always@(edge c) doesn’t unblock as c transitions from x to z which is “No edge” as per LRM

(Q2) What does LRM mean by “non-edge implicit event“ ?

(Q3) Do all the above rules regarding event control apply to event control (@(posedge clk)) used within a concurrent assertion as well ?

(Q4) Is assert property( @(a) seq_expr) different than

assert property( @(edge a) seq_expr) ?

2

@(edge sig) is the same as @(posdege sig or negedge sig)

An X to Z transition is not an edge. See table 9-2 in the IEEE 1800-2023 SystemVerilog LRM.

A “non-edge implicit event” is the change in value of any expression. That expression can more than one-bit. As soon as you add posedge, negedge, or edge, only the LSB changing is considered.

1 Like
3

Thanks Dave.

On (4)

ap1:assert property( @(c) 1 ) $display("T:%0t ap1 pass",$time); 
                         else $display("T:%0t ap1 fails",$time);
    
ap2:assert property( @(edge c) 1 ) $display("T:%0t ap2 pass",$time); 
                              else $display("T:%0t ap2 fails",$time);

I observe T:5 ap1 pass