Fatal: (vsim-8451) C:/modeltech_pe_10.4c/examples/testbench.sv(30): Virtual interface resolution cannot find a matching instance for 'virtual add_sub_if'

UVM
,
1

Hey,
I am new to UVM and model sim.
I try to compile a simple example im modelsim:

I put the uvm-1.2 folder which contains the uvm_pkg in the folder of my project.

I compiled with the following command:
vlog -work work -sv -stats=none C:/modeltech_pe_10.4c/examples/testbench.sv ./uvm-1.2/src/uvm_pkg.sv +incdir+./uvm-1.2/src

I run the simulation with:
vsim work.top

I got the following error:
//

Loading sv_std.std

Loading work.uvm_pkg

Loading work.testbench_sv_unit

** Note: (vsim-8785) UVM-aware debugging capabilities will be disabled since no compiled “questa_uvm_pkg” can be found.

This also means that later if you turn on UVM-aware debugging your debug simulations may have

different random seeds from your non-debug simulations.

Loading work.top

Loading work.ADD_SUB

Loading work.add_sub_if

** Fatal: (vsim-8451) C:/modeltech_pe_10.4c/examples/testbench.sv(30): Virtual interface resolution cannot find a matching instance for ‘virtual add_sub_if’.

Time: 0 ns Iteration: 0 Region: /testbench_sv_unit File: C:/modeltech_pe_10.4c/examples/testbench.sv

FATAL ERROR while loading design

Error loading design

End time: 12:03:21 on Jun 29,2016, Elapsed time: 0:00:00

Errors: 1, Warnings: 0

2

In reply to saritr:

SystemVerilog requires that any virtual interface that gets loaded must have a matching actual interface instantiated somewhere in the design.

So on testbench.sv:9 there is virtual interface of type add_sub_if declared. This error message is saying that vsim didn’t find an actual interface instantiation to match it.

If you go looking for where interface add_sub_if is instantiated, you’ll discover that it is not actually directly instantiated anywhere, instead it is bound to the dut with the bind statement on design.sv:44

So what went wrong?

You may have seen a warning like this when design.sv was compiled

** Warning: (vlog-2650) ‘bind’ found in compilation unit scope. Please use -cuname to ensure that ‘bind’ gets elaborated.

What has happened here is that since the bind statement is outside of any design unit scope, when you told vsim to load the top level work.top, that ended up not including the $unit scope that contained the bind.

This is one reason why I personally do like relying using the $unit scope

So the easiest way around this is to do what the warning message suggests and give the $unit scope an explicit name and load it at vsim time
ie something like

vlog design.sv testbench.sv -cuname my_cu
vsim -c top my_cu