Fatal error in Task ram_test_pkg/ram_wr_monitor::collect_data at ../wr_agt_top/ram_wr_monitor.sv line 94

UVM
,
1

Hello, I am stuck in this error and unable to debug this. Can you please help me with this.

Fatal error in Task ram_test_pkg/ram_wr_monitor::collect_data at …/wr_agt_top/ram_wr_monitor.sv line 94
HDL call sequence:

Stopped at …/wr_agt_top/ram_wr_monitor.sv 94 Task ram_test_pkg/ram_wr_monitor::collect_data

Here is the ram_wr_monitor code.

class ram_wr_monitor extends uvm_monitor;

// Factory Registration
`uvm_component_utils(ram_wr_monitor)


virtual ram_if.WMON_MP vif;
ram_wr_agent_config m_cfg;

extern function new(string name = "ram_wr_monitor", uvm_component parent);
extern function void build_phase(uvm_phase phase);
extern function void connect_phase(uvm_phase phase);
extern task run_phase(uvm_phase phase);
extern task collect_data();
extern function void report_phase(uvm_phase phase);

endclass
//----------------- constructor new method -------------------//
function ram_wr_monitor::new(string name = “ram_wr_monitor”, uvm_component parent);
super.new(name,parent);
endfunction

//----------------- build() phase method -------------------//
function void ram_wr_monitor::build_phase(uvm_phase phase);
super.build_phase(phase);
if(!uvm_config_db #(ram_wr_agent_config)::get(this,“”,“ram_wr_agent_config”,m_cfg))
`uvm_fatal(“CONFIG”,“Config has not been set(), have you set() it”)
endfunction

//----------------- connect() phase method -------------------//
function void ram_wr_monitor::connect_phase(uvm_phase phase);
// super.connect_phase(phase);
vif = m_cfg.vif;
endfunction
//----------------- run() phase method -------------------//
task ram_wr_monitor::run_phase(uvm_phase phase);
forever
begin
collect_data();
end
endtask

// In forever loop
// Call task collect_data provided

// Collect Reference Data from DUV IF
task ram_wr_monitor::collect_data();
write_xtn data_sent;
// Create an instance data_sent
data_sent= write_xtn::type_id::create(“data_sent”);
@(posedge vif.wmon_cb.write);
data_sent.write = vif.wmon_cb.write;
data_sent.data = vif.wmon_cb.data_in;
data_sent.address = vif.wmon_cb.wr_address;
data_sent.xtn_type = (data_sent.address == 'd1904) ? BAD_XTN : GOOD_XTN ;
`uvm_info(“RAM_WR_MONITOR”,$sformatf(“printing from monitor \n %s”, data_sent.sprint()),UVM_LOW)

	m_cfg.mon_rcvd_xtn_cnt++;

endtask

// UVM report_phase

function void ram_wr_monitor::report_phase(uvm_phase phase);
`uvm_info(get_type_name(), $sformatf(“Report: RAM Monitor received %0d transactions”,m_cfg.mon_rcvd_xtn_cnt),UVM_LOW)
endfunction

2

In reply to Akhil9848:

What is line 94?

3

In reply to chr_sue:

@(posedge vif.wmon_cb.write); //This is line 94

(but i do not see any error here)

//Below is the ram interface code.
define RAM_WIDTH 64 define ADDR_SIZE 12

interface ram_if(input bit clock);

logic [`RAM_WIDTH-1 : 0] data_in;       // Data Input
logic [`ADDR_SIZE-1 : 0] rd_address;    // Read Address
logic [`ADDR_SIZE-1 : 0] wr_address;    // Write Address
logic read;                             // Read Control
logic write;                            // Write Control
bit clk;

wire [`RAM_WIDTH-1 : 0] data_out;

assign clk = clock;

modport DUV_MP (input data_in, rd_address, wr_address, read, write, clk,
				output data_out);

//TB Modports and CBs
//Write OVC Driver CB
clocking wdr_cb @ (posedge clock);
	default input #1 output #1;
	output data_in;
	output wr_address;
	output write;
endclocking

clocking rdr_cb @ (posedge clock);
	default input #1 output #1;
	output rd_address;
	output read;
	input data_out;
endclocking


clocking wmon_cb @(negedge clock);
	default input #1 output #1;
	input data_in;
	input wr_address;
	input write;
endclocking

//Read OVC Monitor CB
clocking rmon_cb @(negedge clock);
	default input #1 output #1;
	input data_out;
	input rd_address;
	input read;
endclocking

//Write OVC Driver MP
modport WDR_MP (clocking wdr_cb);
//Read OVC Driver MP
modport RDR_MP (clocking rdr_cb);
//Write OVC Monitor MP
modport WMON_MP (clocking wmon_cb);
//Read OVC Monitor MP
modport RMON_MP (clocking rmon_cb);

endinterface

4

In reply to Akhil9848:
When using clocking blocks you should synchronizer on the cb and not on a signal of the cb