Fatal error in Function ram_test_pkg/ram_rd_agent::build_phase at ../rd_agt_top/ram_rd_agent.sv line 69

UVM
,
1

Hello, I am facing this error and unable to debug this error.

Can you please help me with this.
Fatal error in Function ram_test_pkg/ram_rd_agent::build_phase at …/rd_agt_top/ram_rd_agent.sv line 69

HDL call sequence:

Stopped at …/rd_agt_top/ram_rd_agent.sv 69 Function ram_test_pkg/ram_rd_agent::build_phase

Here is the code for ram_rd_agent.sv

class ram_rd_agent extends uvm_agent;

// Factory Registration
`uvm_component_utils(ram_rd_agent)

    ram_rd_agent_config m_cfg;
   
ram_rd_monitor monh;
ram_rd_sequencer seqrh;
ram_rd_driver drvh;

//------------------------------------------
// METHODS
//------------------------------------------

// Standard UVM Methods:
extern function new(string name = “ram_rd_agent”, uvm_component parent = null);
extern function void build_phase(uvm_phase phase);
extern function void connect_phase(uvm_phase phase);

endclass : ram_rd_agent
//----------------- constructor new method -------------------//

   function ram_rd_agent::new(string name = "ram_rd_agent", 
                           uvm_component parent = null);
     super.new(name, parent);
   endfunction

//----------------- build() phase method -------------------//

function void ram_rd_agent::build_phase(uvm_phase phase);
	super.build_phase(phase);
            // get the config object using uvm_config_db 
  if(!uvm_config_db #(ram_rd_agent_config)::get(this,"","ram_rd_agent_config",m_cfg))
	`uvm_fatal("CONFIG","cannot get() m_cfg from uvm_config_db. Have you set() it? (i am in agent)")  
            monh=ram_rd_monitor::type_id::create("monh",this);	
	if(m_cfg.is_active==UVM_ACTIVE)
	begin
	drvh=ram_rd_driver::type_id::create("drvh",this);
	seqrh=ram_rd_sequencer::type_id::create("seqrh",this);
	end

endfunction

//----------------- connect() phase method -------------------//
function void ram_rd_agent::connect_phase(uvm_phase phase);
if(m_cfg.is_active==UVM_ACTIVE)
begin
drvh.seq_item_port.connect(seqrh.seq_item_export);
end
endfunction

2

In reply to Akhil9848:

What is line69?

3

In reply to chr_sue:

Hi,

if(m_cfg.is_active==UVM_ACTIVE)//This is line no 69

//Below is the code for read RAM agent configuration
class ram_rd_agent_config extends uvm_object;

`uvm_object_utils(ram_rd_agent_config)

// Declare the virtual interface handle for ram_if as “vif”
virtual ram_if vif;
uvm_active_passive_enum is_active = UVM_ACTIVE;

// Declare the mon_rcvd_xtn_cnt as static int and initialize it to zero
static int mon_rcvd_xtn_cnt = 0;

// Declare the drv_data_sent_cnt as static int and initialize it to zero
static int drv_data_sent_cnt = 0;
extern function new(string name = “ram_rd_agent_config”);

endclass: ram_rd_agent_config

function ram_rd_agent_config::new(string name = “ram_rd_agent_config”);
super.new(name);
endfunction

4

In reply to Akhil9848:

Looks like your config object does not exist or does not have the data field is_active.

5

In reply to chr_sue:

Hello, config object is present and also the data field is_active is present in the config class.

still facing the same error

6

In reply to Akhil9848:

Provide the code you set the ram_rd_agent_config.

I got your code working as below.
Look at the set code for the config.
Note: didn’t follow all uvm standard coding guidelines. Just replicated the example.

import uvm_pkg::*;
`include “uvm_macros.svh”
typedef class ram_rd_agent_config;
class ram_rd_agent extends uvm_agent;

// Factory Registration
`uvm_component_utils(ram_rd_agent)

ram_rd_agent_config m_cfg;

//ram_rd_monitor monh;
//ram_rd_sequencer seqrh;
//ram_rd_driver drvh;

//------------------------------------------
// METHODS
//------------------------------------------

// Standard UVM Methods:
extern function new(string name = "ram_rd_agent", uvm_component parent = null);
extern function void build_phase(uvm_phase phase);
extern function void connect_phase(uvm_phase phase);

endclass : ram_rd_agent
//----------------- constructor new method -------------------//

function ram_rd_agent::new(string name = “ram_rd_agent”, uvm_component parent = null);
super.new(name, parent);
endfunction

//----------------- build() phase method -------------------//

function void ram_rd_agent::build_phase(uvm_phase phase);
super.build_phase(phase);
// get the config object using uvm_config_db
if(!uvm_config_db #(ram_rd_agent_config)::get(this,“”,“m_cfg”,m_cfg))
uvm_fatal("CONFIG","cannot get() m_cfg from uvm_config_db. Have you set() it? (i am in agent)") //monh=ram_rd_monitor::type_id::create("monh",this); if(m_cfg.is_active==UVM_ACTIVE) begin uvm_info(get_type_name(), $sformatf(“In build_phase PASS THROUGH m_cfg.is_active==UVM_ACTIVE”), UVM_MEDIUM)
//drvh=ram_rd_driver::type_id::create(“drvh”,this);
//seqrh=ram_rd_sequencer::type_id::create(“seqrh”,this);
end
endfunction

//----------------- connect() phase method -------------------//
function void ram_rd_agent::connect_phase(uvm_phase phase);
if(m_cfg.is_active==UVM_ACTIVE) begin
//drvh.seq_item_port.connect(seqrh.seq_item_export);
`uvm_info(get_type_name(), $sformatf(“In connect_phase PASS THROUGH m_cfg.is_active==UVM_ACTIVE”), UVM_MEDIUM)
end
endfunction

//Below is the code for read RAM agent configuration
class ram_rd_agent_config extends uvm_object;

`uvm_object_utils(ram_rd_agent_config)

// Declare the virtual interface handle for ram_if as "vif"
//virtual ram_if vif;
uvm_active_passive_enum is_active = UVM_ACTIVE;

// Declare the mon_rcvd_xtn_cnt as static int and initialize it to zero
static int mon_rcvd_xtn_cnt = 0;

// Declare the drv_data_sent_cnt as static int and initialize it to zero
static int drv_data_sent_cnt = 0;
extern function new(string name = "ram_rd_agent_config");

endclass: ram_rd_agent_config

function ram_rd_agent_config::new(string name = “ram_rd_agent_config”);
super.new(name);
endfunction

class tmp_test extends uvm_test;
ram_rd_agent m_agnt;
`uvm_component_utils(tmp_test)

function new(string name = "tmp_test", uvm_component parent);
    super.new(name, parent);
endfunction : new

function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    m_agnt = ram_rd_agent::type_id::create("m_agnt", this);
endfunction: build_phase

endclass :tmp_test

module tb();
import uvm_pkg::*;
`include “uvm_macros.svh”
ram_rd_agent_config m_cfg;

initial begin
    m_cfg = ram_rd_agent_config::type_id::create("m_cfg", null);
    uvm_config_db #(ram_rd_agent_config)::set(null,"*","m_cfg",m_cfg);
    run_test("tmp_test");
end

endmodule : t