Hi,
How can we use factory(like in ovm) concept in sv,please any one help me.
Thanks,
Aslam
Hi Aslam,
Well, OVM is SystemVerilog, as is UVM. The factory is an object-oriented programming pattern, so it requires the use of classes in SystemVerilog. In addition, there is a fair amount of infrastructure that is required in order to implement a factory. Therefore, I’d suggest you use UVM (or OVM) if you want to use a factory. Hope this helps,
-Tom
In reply to tfitz:
Hi tfitz,
i got your point,but i think in sv we have the concept called “callbacks” it’s only for the method overriding,is there any class overriding in sv(like factory pattern)?
Thanks,
Aslam
Actually, callbacks are a standard programming practice. There’s nothing explicitly in the SV language called a ‘callback.’
When you extend a class, you have the option of overriding a method or constraint in the base class. To override a constraint, you simply need to create a new constraint with the same name. To override a method, the name of the method, and the argument types must be the same, although you can change what the method actually does. A callback is simply an agreed-upon set of methods that will get called, with a registration mechanism so you can add/delete methods to that set. Again, this requires you to put the infrastructure together to do this. In terms of SystemVerilog, it’s just using OOP.
Without using the factory in UVM, there’s really no good way to override the type of an object in SystemVerilog. Once you do
my_obj m = new();
you’re stuck. Object m will always be of type my_obj. The only flexibility you have would be parameterized classes, where you could do
class my_class #(type t = int);
t m = new();
Then you could instantiate my_class and specify the type:
my_class #(my_obj) = new();
Note that making the default type t be an int (or any non-class type) will cause a compiler error if you don’t override the type.
You of course have to be careful not to write my_class to try and do anything that wouldn’t be appropriate to the ultimate type that you select.
You could do a similar thing with modules (see 1800-2009, 6.20.3):
module ma #( parameter p1 = 1, parameter type p2 = shortint )
(input logic [p1:0] i, output logic [p1:0] o);
p2 j = 0; // type of j is set by a parameter, (shortint unless redefined)
always @(i) begin
o = i;
j++;
end
endmodule
module mb;
logic [3:0] i,o;
ma #(.p1(3), .p2(int)) u1(i,o); //redefines p2 to a type of int
endmodule
Once you start overriding types like this, though, you’re opening yourself up to a lot of headaches and dependencies, so be careful.
Good luck,
-Tom
You might want to read my co-authored DVCon paper that talks about using the factory. Not that I recommend trying to do this without using the OVM/UVM, but the paper was written before the OVM was released, so it does show you the raw mechanism in SV.