Facing a compilation issue

UVM
1

https://www.edaplayground.com/x/5v7c

irun: 15.20-s038: (c) Copyright 1995-2017 Cadence Design Systems, Inc.
class Packet;
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ncvlog: *E,DUPIDN (./packet.sv,1|11): identifier ‘Packet’ previously declared [12.5(IEEE)].
(`include file: adder_intf.sv line 1, file: testbench.sv line 5)
Environment env;
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ncvlog: *E,NOIPRT (testbench.sv,14|16): Unrecognized declaration ‘env’ could be an unsupported keyword, a spelling mistake or missing instance port list ‘()’ [SystemVerilog].
irun: *E,VLGERR: An error occurred during parsing. Review the log file for errors with the code *E and fix those identified problems to proceed. Exiting with code (status 1).

Can anyone help me sort this. I have attached the link to eda playground above. Thank You

2

In reply to sai_pra99:

You are including the file packet.sv at least 2 times. Package your files belonging together in a package this will resolve the issue.

3

In reply to chr_sue:
Thanks for the response.

I am unable to do that It’s throwing an error stating package cannot be bound.

4

In reply to sai_pra99:

Instead of a package you are using only includes. This is a bad ans risky coding style.

5

In reply to sai_pra99:

You need to import the package you compile.

See SystemVerilog Coding Guidelines: Package import versus `include - Verification Horizons

6

In reply to dave_59:

Hi,

Mr. Dave thanks for sharing that piece of information between include and import. It highlights the nitty-gritty details.

I have tried doing everything as instructed/suggested by you both. But still, I face an issue stating “package couldn’t be bound”. I feel this is because of the compilation order.

It would be a great help as a beginner if you review the code once again and fix those (or) help me fix those with a suitable snippet .

Here is my recent modified code with all said:

Your text to link here…