Extracting type of variable within a macro

SystemVerilog
, ,
3

In reply to dave_59:

Thanks for your answer, but it looks like it doesn’t compile with my simulator.

I have:


`define DO_STUFF(var) \
type(var) var``_new; \

module top();

  logic a;

  `DO_STUFF(a)

endmodule

and I compile with:

vcs -sverilog -R experiment.sv

Then I get the error:

Parsing design file 'experiment.sv'

Error-[SE] Syntax error
  Following verilog source has syntax error :
  "experiment.sv", 9 (expanding macro): token is 'type'
    `DO_STUFF(a)
                ^
  System verilog  keyword 'type' is not expected to be used in this context.

#0, DO_STUFF(var=a) : "experiment.sv":3
full expansion of macro (DO_STUFF), error at line 1
=>type(a) a_new; 
  
1 error
CPU time: .052 seconds to compile

Any other ideas?