In reply to sylvainb:
Thanks sylvainb.
I did a little bit more search on this. It seems systemverilog/uvm supports this, you CAN override a member/property in a base class. As I indicated above, if the class member is of type uvm_object, above code can work. However per expert like Dave Rich @dave_59, this is a very bad programming practice. https://verificationacademy.com/forums/systemverilog/setting-variables-same-name-child-class. And moving to uvm_component member, it doesn’t work at all.
But I think this kind of inheritance does provide value. It is something like factory but can’t be resolved by factory. I want to keep the same name slv so that any code manipulating slv in base class will be reused. If I use a different name, same logic need be implemented again.