Setting variables with same name from child class

SystemVerilog
1

Hi,

class Packet; // base class
integer value;
endclass

class LinkedPacket extends Packet; // derived class
integer value;
endclass

In the above example, I have two classes, one is parent and other is child class. As far as I know, parent’s property value is also present in LinkedPacket.Correct me if Iam wrong?

I want to assign some value to both the property “integer value” of Packet class and also the property of LinkedPacket Class by taking the object of LinkedPacket. Please suggest me How can I do it?

2

It is an extremely bad programming practice to have properties with the same name in a base and extended class. It will be and endless source of confusion, especially when you start involving constraints.

Also, pleas avoiding the terms parent and child when referring to a base and extended class types. It implies they are separate objects. The LinkedPacket type includes all the properties of Packet, and when you construct a LinkedPacket object, you get only one object.

If you really think you need to do this, then you can assign a LinkedPacket object handle to a Packet class variable. The you can access the Packet class properties.

packet P;
LinkedPacket LP;

...
LP = new;
LP.value = 1;
P = LP;
P.value = 2;