Expression bit length determination with cast

SystemVerilog
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2

In reply to verifsc:

Here is what I thought the last $display does:

  1. 1 << addr_width yields a 32 bit signed result. The value is 0.
  2. (1 << addr_width) -1 yields a 32 bits signed result. The value is -1.
  3. my_type’( ((1 << addr_width)-1)) casts “-1” to my_type which is an unsigned 64 bit data type. It should pad the 32 bits signed value (-1) with 0s to 64 bits. The value should be 'h0000_0000_ffff_ffff.