I just wanted to know if anyone is aware of a method to exclude fields/bits within registers from UVM built-in RAL reset/bitbash testing. I know that there are ways to exclude registers from these built-in tests by setting resources (“NO_REG_TESTS”, “NO_REG_HW_RESET_TEST” etc).
Is there a similar way to exclude fields/bits within registers that anyone is aware of?
Alpesh,
I saw your comments about chaning .xml file. But lets say we have a register with RO type & if we have to ignore the compare in that case option we have to use some thing like (“<REG_FIELD>.NO_RAL_TEST”,1)
I have been exploring this issue as well, and the unfortunately answer is no unless you want to alter the UVM sequences.
This is perhaps and oversight in the built in bit bash sequences by UVM and I would expect it to be fixed in the next revision. Currently the bit bash sequence does not pay attention to the writeable attributes of the register fields.
My intention next week is to either extend the sequence and overwrite the necessary method or accept the error I know about for my register model and suppress them from the final reporting phase.
I copied the bit bash code into my own customized sequence. In body task, I set dc=1 as below.
foreach (maps [j]) begin
foreach (fields [k]) begin
…
case (fields[k].get_access(maps[j]))
“WO”, “WOC” , “WOS”, “W1S” : dc = 1 //This will discard checking of all register field with these access.
endcase
. . .
end
Also I used string operation to discard checking on Reserved field.
my_field_sub = my_field.substr (my_field.len()-5, my_field.len() -2)
if (my_field_sub == “RSVD” || my_field_sub == “_RSVD”) dc =1 ;