Hello
I have built a simple UVM validation environment for a VHDL IP block. Currently the environment is pretty much a skeleton (ie no monitors, sequencesrs, scoreboards drivers etc are defined). However, i have defined the virtual interfaces, skeleton {Configuration, Environment} and a simple test case.
I have built this environment from reading a few UVM tutorials. Obviously, each tutorial has a different way of building the validation environment.
I have managed to write an empty test case (just prints out messages) and managed to compile and execute it okay.
Before i move to the next step of writing the sequencers, drivers etc to wiggle the DUT’s pin, i am trying to understand the different ways that the {Environment, configuration, testcases, virtual interface} can be written and more importantly how these different components connect together in a “classic” UVM validation environmnet.
Does anyone have any pointers to how to build a “classic” UVM validation environment?
My biggest confusion is
a) where to declare the virtual interfaces
b) how to pass the instance information for the virtual interface to the other components in the validation environment.
I have seen different ways that other people have done, but don’t understand the reasons behind these different ways.
Any thoughts/pointers much appreciated.
Thanks
JO