Example for testing transport path delay control doesn't work as expected

SystemVerilog
1

I created a simple example for testing +transport_path_delays and +pulse_r/0, but it just doesn’t work as expected.

Anybody can help me?

% vlog top.v
% vsim -novopt +transport_path_delays +pulse_r/0 top

but signal “clk_delayed” is always ‘x’.

`timescale 1ns/1ps
module top;
reg clk;
wire clk_dlyed;

initial begin
   clk = 0;
   forever #0.4 clk = ~clk;
end

assign #0.6 clk_dlyed = clk;
endmodule
2

Do not use -novopt

Thew switches +transport_path_delays and +pulse_r/0 only work on specify block path delays, no on the delay of a continuous assignment.

3

In reply to dave_59:

Hi Dave,

Thanks for helping clarify the usage of these option.

Btw, can you explain more on why “don not use -novopt”? Is it related with my example or just common recommendation?

thanks,
Xiaofei

4

In reply to xbluewing:

A common recommendation. In a future version of Questa,you will get a message that looks something like

WARNING: YOU ARE RUNNING WITH ALL OPTIMIZATIONS TURNED OFF. YOUR SIMULATION WILL RUN VERY SLOOOOOOWLY. If you are doing this for waveform/PLI visibility, check the User Guide for MUCH more efficient ways of preserving visibility.