Event triggering in SV

SystemVerilog
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2

In reply to rahul19190:

Please use code tags making your code easier to read. I have added them for you.

The event triggered method only returns true in the timeslot where the event in triggered. It returns false once time advances. There is a non-blocking event trigger that you can avoid a race between the two initial blogs. It works very similar to a non-blocking assignment.

module event_l;
string testname;
event e;
 
initial begin
  @(e);
  case(testname)
  "gd_pkt":begin
            $display("i am in good pkt");
          end
  "bd_pkt":begin
	    $display("i am in bd pkt");
	   end
  "ill_pkt":begin
           $display("i am in ill pkt");
            end
  endcase
end
 
initial begin
  $value$plusargs("testname=%s",testname);
  ->>e;
end
endmodule