Event region for if condtion evaluation

SystemVerilog
,
1

I am not sure whether in which region does if condition evaluation will be done.

Can any one help me in finding out the output for below code snippet -

module test();
   logic [3:0] a = 5;

    initial begin
       #5;
       a = 10;
    end

    initial begin
       #5;
       if (a == 10)
          $display("if condition is evaluated after activ region");
       else 
          $display("if condition is evaluated before active region");
    end

endmodule

i had checked the output of above code with vcs where it is displaying – “if condition is evaluated before active region”. does that mean if condition will be evaluated with values of postponed region of previous time stamp.

2

In reply to raghavender.yalal:

All the code you show executes in the active region. You have a race condition because there is no guaranteed event ordering between the two initial process, only that the code within each begin/end block executes in serial order.

To remove the race, you either need to change one of the #5 delays, or change the assignment to ‘a’ to a non-blocking assignment (NBA).