Event Control V/S $rose

SystemVerilog
,
1

I was trying to understand differences between :: @( posedge Sig ) V/S $rose( Sig ) ::

(1) $rose( Sig ) checks that LSb of Sig changes from 0 / X / Z to 1 whereas

 @( posedge Sig )  will  be  triggered  whenever  Sig  changes  from  0 / X / Z  to  1  OR  even  **0  to  X / Z** .

(2) $rose( Sig ) returns 1’b0 / 1’b1 and hence can be used as an argument to System function like $display / $sformatf

 whereas  @(  posedge  Sig )  can't  be  used  as  argument  to  System  function  like  $display / $sformatf  **as  it  doesn't  return  anything**

I have some confusion regarding the below 3rd difference as LRM’s wordings are a little confusing ::

(3)


LRM  9.4.2  ::   An implicit event shall be detected on any change in the value of the expression. An edge event shall be detected only on the LSB of the expression. A change of value in any operand of the expression without a change in the result of the expression shall not be detected as an event.

So if 2-bit variable Sig changes from default value 2’bXX to 2’b1X , should @( posedge Sig ) be triggered ?

i.e Sig[1] changes from X to 1 whereas LSb remains at X .


logic [1:0]  Sig  ;

always @( posedge Sig )  $display(" TIME : %0t  posedge @( Sig )  triggered  " , $time) ;

 initial  begin
    #4 ; Sig = 2'b1X ; //  TIME : 04  .  Sig[1]  Changes  from  X  to  1  !!  

    #6 ; Sig = 2'b11 ; //  TIME : 10
  end

Any further differences I have missed out on ?

2

In reply to hisingh:



logic [7:0 address,data;

always @(address) // triggers change on any bits of vectors

always @(posedge address) // triggers only change in the lsb of the vector