Error while simulating system verilog code in Questasim 15.0 on Linux platfrom

SystemVerilog
1

Hello All, can anyone solve this error while simulating the system verilog code for counter.

The error is showing as follows:

 ** Fatal: Unexpected signal: 11.
# ** Error: /home/remote/home/spandana/Desktop/my/trail.sv(152): Vopt Compiler exiting
# ** Error: (vopt-2064) Compiler back-end code generation process terminated with code 211.

And the line 152 is showing endmodule.

Thanks
Spandana

2

In reply to spandana kaarri:
This forum is not for tool specific issues. You should contact your local support team if you need additional support.