In reply to hdlcohen:
Ok thank you very much to both of you, Ben and Hdlcohen.
I will check all the links that Ben shared, actually I am using Questa from Mentor, we have the suit tool for our university.
An super scalar processor was done with Verilog and now I am writing that same core with System Verilog so I am checking code here and there to acquire that knowledge by practice so I can quickly implement this cpu. The other thing that I want to do is to do first verification with System Verilog and then using UVM. If you some extra links to reach my goal I will really appreciate.
Regarding the always_ff I already changed for always and it works! ;)
I was thinking what system verilog says, you have to use the always_ff module but I think there is not a problem if I use only always for my cpu synthesis.
Thank you again, all the best to you guys,