Error in constraint number of ones in stream is more than 4

SystemVerilog
,
1

My question is number of ones in 8 bit vector is more than 4
for example : a = 0101_1010 or 1111_0000 or 0111_1101
I am facing issue randomization failure because of constraints overlap

// Code your testbench here
// or browse Examples
class ones;
  rand bit [7:0] a;
  rand bit [2:0] l;
  constraint l_c 	{
    l > 4;
    l < 6;
    solve l before a;
  }
  
  constraint a_c	{
    count_ones(a) > l;
  }
  
  	function int count_ones ( bit [9:0] w );
		for( count_ones = 0; w != 0; w = w >> 1 )
			count_ones += w & 1'b1;
	endfunction
  
endclass

module top;
  ones s;
  initial
    begin
      s =new();
      assert(s.randomize());
      $display(" a= %b, b= %d", s.a, s.l);
    end
endmodule

my transcript is below can any one help me solve this we can easly solve with $countones but I dont want to use that function.
output :
QuestaSim-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
Start time: 21:35:44 on Jul 29,2023
vlog -writetoplevels questa.tops -timescale 1ns/1ns design.sv testbench.sv
– Compiling package testbench_sv_unit
– Compiling module top

Top level modules:
top
End time: 21:35:44 on Jul 29,2023, Elapsed time: 0:00:00
Errors: 0, Warnings: 0

vsim top -batch -do “vsim -voptargs=+acc=npr; run -all; exit” -voptargs=“+acc=npr”

Start time: 21:35:44 on Jul 29,2023

** Note: (vsim-3812) Design is being optimized…

// Questa Sim-64

// Version 2021.3 linux_x86_64 Jul 13 2021

//

// Copyright 1991-2021 Mentor Graphics Corporation

// All Rights Reserved.

//

// QuestaSim and its associated documentation contain trade

// secrets and commercial or financial information that are the property of

// Mentor Graphics Corporation and are privileged, confidential,

// and exempt from disclosure under the Freedom of Information Act,

// 5 U.S.C. Section 552. Furthermore, this information

// is prohibited from disclosure under the Trade Secrets Act,

// 18 U.S.C. Section 1905.

//

Loading sv_std.std

Loading work.testbench_sv_unit(fast)

Loading work.top(fast)

vsim -voptargs=+acc=npr

run -all

testbench.sv(28): randomize() failed due to conflicts between the following constraints:

testbench.sv(7): l_c { (l > 4); }

testbench.sv(13): a_c { (this.count_ones(a) > l); }

Where:

this.count_ones(a) = 3

Given:

bit [2:0] l

** Note: (vsim-7130) Enabling enhanced debug (-solvefaildebug=2) may generate a more descriptive constraint contradiction report and -solvefaildebug testcase.

** Note: (vsim-7106) Use vsim option ‘-solvefailtestcase[=filename]’ to generate a simplified testcase that will reproduce the failure.

** Warning: (vsim-7084) No solutions exist which satisfy the specified constraints; randomize() failed.

Time: 0 ns Iteration: 0 Process: /top/#INITIAL#25(#ublk#31584#26) File: testbench.sv Line: 28

** Error: Assertion error.

Time: 0 ns Scope: top File: testbench.sv Line: 28

a= 00000000, b= 0

exit

End time: 21:35:45 on Jul 29,2023, Elapsed time: 0:00:01

Errors: 1, Warnings: 1

2

In reply to marathuteja:

Calling user-defined function in constraints should be done carefully, because the function shall be called before constraints are solved (no back-track done by the solver to find proper function input), and this is a source potential constraints conflicts.

3

In reply to M.Wafa:

I this how can i proceed further can you please help me m. Wafa

4

In reply to marathuteja:

Use the built-in $countones function instead :


constraint a_c	{ $countones(a) > l ; }