Hi,
I am currently trying to integrate the UVM Register model with the reg adapter and reg predictor (uvm_reg_predictor). The Bus protocol for the test case is AHB.
I am stuct at connecting the predictor to the bus agent’s analysis port.
I am doing the below:
// Connect the predictor to the bus agent monitor analysis port
m_m0s8peri_env.ahb_master_agent[0].ap[“master_single_transfer_ap”].connect(ahb2reg_predictor.bus_in);
Following is the error I am getting:
** Error: (vsim-3978) /proj/gpfs/xzk/wa_peri/xzk_vm0s8peri_dev_119/vm0s8peri/tb/fnv/tests/common/m0s8peri_tc_base.svh(184): Illegal assignment to class /proj/gpfs/xzk/wa_peri/xzk_vm0s8peri_dev_119/vm0s8peri/tb/fnv/lib/work_tb_RTL.uvm_pkg::uvm_port_base #(class /proj/gpfs/xzk/wa_peri/xzk_vm0s8peri_dev_119/vm0s8peri/tb/fnv/lib/work_tb_RTL.uvm_pkg::uvm_tlm_if_base #(class /proj/gpfs/xzk/wa_peri/xzk_vm0s8peri_dev_119/vm0s8peri/tb/fnv/lib/work_tb_RTL.mvc_pkg::mvc_sequence_item_base #(mvc_sequence_item_base), class /proj/gpfs/xzk/wa_peri/xzk_vm0s8peri_dev_119/vm0s8peri/tb/fnv/lib/work_tb_RTL.mvc_pkg::mvc_sequence_item_base #(mvc_sequence_item_base))) from class /proj/gpfs/xzk/wa_peri/xzk_vm0s8peri_dev_119/vm0s8peri/tb/fnv/lib/work_tb_RTL.uvm_pkg::uvm_analysis_imp #(class /proj/gpfs/xzk/wa_peri/xzk_vm0s8peri_dev_119/vm0s8peri/tb/fnv/lib/work_tb_RTL.mgc_ahb_v2_0_pkg::ahb_master_single_transfer #(1, 1, 1, 32, 32, 32), class /proj/gpfs/xzk/wa_peri/xzk_vm0s8peri_dev_119/vm0s8peri/tb/fnv/lib/work_tb_RTL.uvm_pkg::uvm_reg_predictor #(class /proj/gpfs/xzk/wa_peri/xzk_vm0s8peri_dev_119/vm0s8peri/tb/fnv/lib/work_tb_RTL.mgc_ahb_v2_0_pkg::ahb_master_single_transfer #(1, 1, 1, 32, 32, 32)))
Time: 0 ps Iteration: 0 Region: /m0s8peri_tc_pkg File: /proj/gpfs/xzk/wa_peri/xzk_vm0s8peri_dev_119/vm0s8peri/tb/fnv/tests/common/m0s8peri_tc_pkg.sv
** Error: (vsim-8754) /proj/gpfs/xzk/wa_peri/xzk_vm0s8peri_dev_119/vm0s8peri/tb/fnv/tests/common/m0s8peri_tc_base.svh(184): Actual input arg. of type ‘class /proj/gpfs/xzk/wa_peri/xzk_vm0s8peri_dev_119/vm0s8peri/tb/fnv/lib/work_tb_RTL.uvm_pkg::uvm_analysis_imp #(class /proj/gpfs/xzk/wa_peri/xzk_vm0s8peri_dev_119/vm0s8peri/tb/fnv/lib/work_tb_RTL.mgc_ahb_v2_0_pkg::ahb_master_single_transfer #(1, 1, 1, 32, 32, 32), class /proj/gpfs/xzk/wa_peri/xzk_vm0s8peri_dev_119/vm0s8peri/tb/fnv/lib/work_tb_RTL.uvm_pkg::uvm_reg_predictor #(class /proj/gpfs/xzk/wa_peri/xzk_vm0s8peri_dev_119/vm0s8peri/tb/fnv/lib/work_tb_RTL.mgc_ahb_v2_0_pkg::ahb_master_single_transfer #(1, 1, 1, 32, 32, 32)))’ for formal ‘provider’ of ‘connect’ is not compatible with the formal’s type ‘class /proj/gpfs/xzk/wa_peri/xzk_vm0s8peri_dev_119/vm0s8peri/tb/fnv/lib/work_tb_RTL.uvm_pkg::uvm_port_base #(class /proj/gpfs/xzk/wa_peri/xzk_vm0s8peri_dev_119/vm0s8peri/tb/fnv/lib/work_tb_RTL.uvm_pkg::uvm_tlm_if_base #(class /proj/gpfs/xzk/wa_peri/xzk_vm0s8peri_dev_119/vm0s8peri/tb/fnv/lib/work_tb_RTL.mvc_pkg::mvc_sequence_item_base #(mvc_sequence_item_base), class /proj/gpfs/xzk/wa_peri/xzk_vm0s8peri_dev_119/vm0s8peri/tb/fnv/lib/work_tb_RTL.mvc_pkg::mvc_sequence_item_base #(mvc_sequence_item_base)))’.
I am not able to figure out exactly what is going wrong? Please guide.