rahu
1
please look into the issue it is showing 0 connection for driver
Fatal: (SIGSEGV) Bad handle or reference.
Time: 0 ns Iteration: 61 Process: /uvm_pkg::uvm_task_phase::execute/fork#143(#ublk#215181159#143)_f6dae6f File: /mentor2020/questasim/linux/…/verilog_src/uvm-1.2/src/tlm1/uvm_sqr_connections.svh
Fatal error in Task uvm_pkg/uvm_sqr_if_base::get_next_item at /mentor2020/questasim/linux/…/verilog_src/uvm-1.2/src/tlm1/uvm_sqr_ifs.svh line 59
HDL call sequence:
Stopped at /mentor2020/questasim/linux/…/verilog_src/uvm-1.2/src/tlm1/uvm_sqr_connections.svh 45 Task uvm_pkg/uvm_sqr_if_base::get_next_item
called from ahb_drv.sv 31 Task top_sv_unit/ahb_drv::run_phase
called from /mentor2020/questasim/linux/…/verilog_src/uvm-1.2/src/base/uvm_common_phases.svh 269 Task uvm_pkg/uvm_run_phase::exec_task
called from /mentor2020/questasim/linux/…/verilog_src/uvm-1.2/src/base/uvm_task_phase.svh 152 Function uvm_pkg/uvm_task_phase::execute
In reply to rahul19190:
check whether driver & sequencer ports are connected in agent connect phase.
driv.seq_item_port.connect(seqr.seq_item_export);
Regards,
Shanthi V A
www.maven-silicon.com
rahu
3
yes they are connected properly…but i am not getting why it is behaving like this.
In reply to rahul19190:
Could you please show your agent code. I want to see what you are doinhg there.
rahu
5
In reply to chr_sue:
Thanks ,
I got it, Actually i have 2 agent master and slave and i was calling sequence without differentiating Mater and slave agent driver.
Thanks