Hi,
I design a FSM in traditional Verilog modelling.But while going through SystemVerilog I found out that that parameter in Verilog can easily be replaced by using enum in SV.My query is that apart from the shortening of length in SV,is there any other advantage of using enum instead of parameter in designing FSM.
-Thanks
In reply to sougata_asic:
There are a couple of advantages of using a enum for an FSM:
- enums offer some amount of type safety. When you declare your FSM state variable using an enum type, you can only assign it with enum labels of that type directly.
- Enums have next(), prev(), and first() methods for traversal. You should check to see if your synthesis tool supports this
- For your testbench or debugging, there is a name() method to get the name of the label as a string for printing.