ENUM typecasting

SystemVerilog
1

There is this statement in SV 2017 IEEE std.

Enumerated variables are type-checked in assignments, arguments, and relational operators. Enumerated variables are auto-cast into integral values, but assignment of arbitrary expressions to an enumerated variable requires an explicit cast.

Does this mean that, I have to do explicit typecasting of the conditional expression statement in the following code snippet?

typedef enum logic [1:0] {
   IDLE, TRANSFER, ACK, NACK
}  state_t ;
state_t curr_state, nxt_state ; 
logic is_ack_received ;

always_comb begin
   case (curr_state)
...
      nxt_state = (is_ack_received)? ACK : NACK ; // Throws compiler error
...
   endcase
end

The compiler which I use (iverilog) forces me to use, saying explicit type casting is required since the condition uses a 4 state logic variable.

nxt_state = state_t'((is_ack_received)? ACK : NACK) ;

Is this required to do so as per the LRM?

2

I think this is underspecified in the LRM. Other tools do not throw an error, but I think you could interpret it to require a cast since the result 2’bxx is not a valid value for the enum. I filed 8482.

3

Thanks Dave. Let me know when there is an update to this issue.