Enum type strong typing rules

SystemVerilog
1

Hi,

I have a following piece of code from my uvm environment

typedef enum {A,B,C} violate; // declared commonly using `include in both packet and driver class.

// dynamic array of this enum type is declared

rand violate violate_e; // its size is constrained in my packet class.

// in my sequence class i am writing a sequence//

uvm_create req.violate_e.rand_mode(0); req.violate_e.contraint_mode(0); req.violate_e = new[1]; req.violate_e[0] = A; or req.violate_e[0] = violate'(A); // enum assignment. uvm_send

// I am able to achieve the desired operation from violate_e and its value but it gives me an elaboration warning with one eda provider
while in mentor graphics simulator its giving an elaboration error.Please help me with a workaround or better way to implement this.

ERROR Msg : Illegal assignment to type packet.enum from type sequence.enum . An enum variable may only be assigned the same enum typed variable or one of its values.

2

When you `include a typedef declaration, it becomes part of the scope where it is included.

You should `include it as part of your package (and not part of your class), and then import the class where necessary.