Enum parameterized declaration

SystemVerilog
,
1

Hello,
I am trying to implement parameterized enum names.
I tried implemented using following 2 ways:

  1. Using define macro, it was successful. Ex: define x 4
    module enum_try (… );
    enum { name} e_list;
    …
    …
    endmodule

2)using parameter, it give error expecting integral value
Ex:
module enum_try #(
parameter x = 4)
(…) ;
enum { name} e_list;
…
…
endmodule

is there an alternative to use get value from parameter
to declare enum in this WAY?

2

In reply to ankitjain:

This feature is an oddity in SystemVerilog as it generates names that cannot be referenced like an array. It works like macro iteration, but there is no macro iteration feature in SystemVerilog.

If you show us how you are expecting to use this, perhaps there in an alternative data type you could use.

3

Enum in this case are used to declare names of state for a fsm. The no of states are to be parameterized based on a parameter passed by another module instantiating it.

4

In reply to ankitjain:
Please show how you expect to use the states in the FSM code. You have to hard code Name0, Name1, Name2 anyways.