Hello, Is there any SV provided feature to swap endianness of a 256 bit variable? for a 32bit example, the code is less: assign data_swapped = {{data[07:00]}, {data[15:08]}, {data[23:16]}, {data[31:24]}}; but too much to type in (error prone) for 256 bit. please advise. Thanks

In reply to UVM_learner6 : assign data_swapped = {<<8{data}}; See section 11.4.14 Streaming operators (pack/unpack) in the IEEE 1800-2017 SystemVerilog LRM .

Endianness swap

SystemVerilog

UVM_geek May 5, 2023, 7:34am 4

Hi ,

For 12345678 input ,the output is 78563412 not 87654321.

How to achieve 87654321.

Thanks