`elsif vs `elseif and unexpected behavior

SystemVerilog
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1

I had some code, something like this

`ifdef A
    // do A
`elsif B
    // do B
`elsif C
    // do C
`else
    $display("alert user they need to use a +define");
`endif

and I wanted to add a new case, and probably get rid of the `else case… so I quickly coded a new ‘else’ like this:

`ifdef A
    // do A
`elsif B
    // do B
`elsif C
    // do C
`elseif D
    // do D
`else
    $display("alert user they need to use a +define");
`endif

and even though I used

+define+D

, the code compiled and simulated with the unexpected “alert user they need to use a +define”.

What???

I delete my compiled output, recompile… same thing. I checked to ensure the +define matched the “else” constant… same. I start wondering about stupid UTF-8 vs ASCII character mismatch (sometimes this happens if you copy code or command-line strings from Microsoft Outlook, or rich-text wiki pages).

Then suddenly I catch a single-character difference… the second “e” in “elseif” doesn’t match the prevailing pattern in my code, which uses “elsif” with no second “e”. So I google

"elseif" vs "elsif" systemverilog

and find this page which doesn’t tell me anything obviously significant… but I figure OK, they are both apparently legal, unless that PDF has a typo.

Seems worth it to try removing the extra “e”.

Code works now as expected.

So now I’m left wondering, why didn’t the compiler error, and since there was no error there must be a good reason, so what’s the reason?

Hope this post saves someone else from losing sleep and a day of effort.

2

In reply to ntmccork:

That was a typo that was corrected in later versions of the standard. But it seems that some tools allow the typo, other tools don’t.