In reply to dave_59:
In reply to ben@SystemVerilog.us:
There are other ways of addressing this:
- packed unions
- aliases
- macros
It really depends on what the intended meanings of the ranges are.
Hi Dave,
First thanks for the suggestion with the “let” construct to be agnostic to variable name.
Could you please elaborate more on how packed unions, aliases or macros may address the bits ranges with agnostics to the variable?
Regards aliases in SV, read it is mainly used to connect nets/wires/ports in modules, please correct me if I am wrong?
So how can it be used in SV classes?
Thanks!
Michael