Elegant way to define range of bits

SystemVerilog
,
4

In reply to Michael54:

Ben’s code was close.

package common_place;

  let FIRST_RANGE(v) = {v}[28:24];
  let SECOND_RANGE(v) = {v}[17:12];

endpackage 


import common_place::*;
...
expected_txn.raw_data[rgb_pos-:5] = FIRST_RANGE(data_range_bus);
expected_txn.raw_data[rgb_pos+6-:6] = SECOND_RANGE(data_range_bus);