Elegant way to define range of bits

SystemVerilog
,
2

In reply to Michael54:
May not be what you exactly want, but it’s a step in the right direction.


//xpected_txn.raw_data[rgb_pos-:5] = data_range_bus[28:24];
//expected_txn.raw_data[rgb_pos+6-:6] = data_range_bus[17:12];
module m;
  bit[31:0] v;
  let FIRST_RANGE =v[28:24];
  let SECOND_RANGE=v[17:12];
  
  initial begin
    FIRST_RANGE= 5'b11111;
    SECOND_RANGE=6'b110011;
    $display("v= %b", v);
  end
endmodule
// run 1ns
// # v= 00011111000000110011000000000000

    //expected_txn.raw_data[rgb_pos-:5] = data_range_bus[FIRST_RANGE];
    // expected_txn.raw_data[rgb_pos+6-:6] = data_range_bus[SECOND_RANGE];

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
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