Elaboration issue with inout connection

SystemVerilog
1

Iam simulating below code
///////////////////////////////Code////////////////////////////////
module b(inout x_inout,inout y_inout,z_inout);

initial begin
$display(“Hai Iam in Instance of top”);
end
endmodule

module a(input x, output y);
b b_inst(
.x_inout(x),
.y_inout(y),
.z_inout({z,1’bz})
);
endmodule
///////////////////////////////Code////////////////////////////////

bharath@xhd-lin64re101-297% vlog -sv a.sv
QuestaSim-64 vlog 10.2b_1 Compiler 2013.06 Jun 7 2013
– Compiling module b
– Compiling module a

Top level modules:
a
bharath@xhd-lin64re101-298% vsim -c a
Reading /mtitcl/vsim/pref.tcl

10.2b_1

vsim -c a

** Note: (vsim-3812) Design is being optimized…

** Error: (vopt-3053) a.sv(13): Illegal inout port connection for “‘z_inout’ (3rd connection)”.

Optimization failed

Error loading design

Error loading design

This elaboration issue iam getting when i run using questasim10.2b_1

2

You can’t connect a literal constant to an inout port.

And why do want to connect a 2-bit concatenation {z,1’bz}, where z is undeclared 1-bit wire, to a 1-bit z_inout port.

It is good practice to explicitly declare all of your port types.

3

inout port expressions must support continuous assignment, so you shouldn’t assign 1’bz to a port. Some simulators will error, while others will show a warning. Also, as dave_59 mentioned, you need a 1-bit connection.

I got it working with these changes:

wire z; // NEW
  assign z = 1'bz; // NEW

and

.z_inout(z) // CHANGE

Full code with sim results is on EDA Playground