Efficient way to convert unpacked array to packed array and vice versa

SystemVerilog
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1

what is the efficient way to convert unpacked arrays to packed arrays and vice versa?

I need to switch between packed to unpacked and also unpacked to packed due to some protocol requirements. I can get it working using for loops but interested in learning more efficient ways if exist.

Here is an example. The no of bits is the same and i need to quickly move between packed to unpacked and vice versa without for loops. Basically looking for the most efficient solution.

logic [3:0] unpacked_array [6:0][7:0];
logic [223:0] packed_array;

2

In reply to hsam:

The most efficient and safest way is using a bitstream cast. (Section 6.24.3 Bit-stream casting in the IEEE 1800-2017 SystemVerilog LRM)

typedef logic [3:0] my_unpacked_type [6:0][7:0];
typedef logic [223:0] my_packed_type;

my_unpacked_type unpacked_array;
my_packed_type   packed_array;

unpacked_array = my_unpacked_type'(packed_array);
packed_array.  = my_packed_type'(unpacked_array);

The bitstream cast requires the source and target types have the exact same number of bits–you get a compiler error otherwise.

This kind of cast only has one algorithm for bit ordering in that unpacked_array[6][7] maps to the MSBs of packed_array, and unpacked_array[0][0] maps to the LSBs of packed_array. If you need a different ordering, you can use the streaming operator (section 11.4.14 Streaming operators (pack/unpack) in the LRM)