In reply to chr_sue:
This is wrong. The run_test() task is designed so that all of the simulation initial blocks are executed prior to starting the build_phase(). This is done specifically to ensure that all config_db:set() calls are completed prior to the UVM environment calling get() in uvm_test_top.
The EDA playground link is no longer available for review, but you should make sure that both hvl_top and hdl_top are executed as top level modules. Also, try different simulators as it is possible that issues may be masked by the simulator you have selected.