In reply to mr.kry:
Thank you shanthi for the response
one more doubt is that why we are taking valid bit differently in different clock pulse,when valid is 0 why we are not driving input signal a &b, and which posedge of clk will run first among the three?
The logic to Drive the data on to interface depends on the DUT protocol, so for driving logic refer to the DUT protocol that you are verifying.
And secondly, as the driving logic is enclosed within begin end block the code executes sequentially.