Thank you shanthi for the response
one more doubt is that why we are taking valid bit differently in different clock pulse,when valid is 0 why we are not driving input signal a &b, and which posedge of clk will run first among the three?
Thank you shanthi for the response
one more doubt is that why we are taking valid bit differently in different clock pulse,when valid is 0 why we are not driving input signal a &b, and which posedge of clk will run first among the three?