Drive signal sync and async both at the same time

SystemVerilog
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1

what will happen if i drive 1 in one signal named as request in this code … sync and async at the same time in same module / program ?
please see this code , then you will get an good idea about what i am trying to ask ?

interface arb_if(input bit clk);
	logic [1:0] grant, request ;
	logic rst;
	clocking cb @(posedge clk);
	output request ;
	input grant;
	endclocking 
	modport TEST (output request, rst,input grant, clk);
    end interface

    module test(arb_if.TEST t1);
      initial begin
        arb_if.cb.request <= 2’b01;      //sync
   
        arb_if.request <= 2’b01;         //async
  end
    endmodule
2

In reply to meet_hmt:

A clocking block output sets up an independent process that schedules an assignment to its variable in the re-NBA region. Any other assignment you make to the same variable happens regardless of what the clocking block does; basically last write wins. In your example, even though you execute the clocking block drive statement and NBA assignment at the same time, the clocking block drive to the variable does not happen until after the clocking block event (posedge clk) and then not until the re-NBA region.