Would it be possible to export to C a task defined inside a SystemVerilog class as the following? When this class is instantiated multiple times, does send get treated as a separate task in each instance of the class? Thanks.
class packet_bfm_t;
int id = 0;
export “DPI-C” task send; // Is this possible and legal to call from C code?
function new (int my_id = 0);
id = my_id;
endfunction : new
My actual problem is this, I have an array of four orthogonal packet senders with task send() defined similar to the code snippet above
class packet_sender_t;
int id;
function new (int mid);
id = mid;
endfunction
task send (int data);
#2ns;
endtask
endclass
parameter NUM_PORTS = 4;
**packet_sender_t packet_sender [NUM_PORTS];
**
How would I call a particular send task from the C code which knows the index of the packet_sender to send. The main thing is I don’t want to write four wrappers for four packet_sender_t.
Would module (instantiated using loop generate construct) with embedded task work in this case to handle parallel streams of packets?
module new_packet_sender_t;
task send(int data);
#2ns;
endtask
endmodule
genvar i;
for (i = 0; i < NUM_PORTS; i++) begin : scope
new_packet_sender_t new_packet_sender[i]();
end
there are many ways to associate your packet senders. My method used self-registration, but it can certainly be done externally outside the class or within a module. Calling a module instanciated task requires a scope based context. You might want to see the example I posted here: