Doubt in randomization using verilog code

SystemVerilog
, ,
1

Hi,

I am trying to just write a simple code in verilog to randomize an addr different ways as shown below:

module Tb(); 
integer add_2; 
reg [31:0]add_1; 
integer add_3; 
initial 
begin
 
repeat (5) 
begin
  #1;
  add_1= $random % 10;
  add_2= {$random} %10 ;
  add_3= $unsigned($random) %10 ; 
end
 
end
 
initial
 $monitor("add_3 = %0d;add_2 = %0d;add_1 = %0d",add_3,add_2,add_1); 
endmodule

The result is as shown below for the above code:
add_3 = x;add_2 = x;add_1 = x
add_3 = 7;add_2 = 7;add_1 = 8
add_3 = 7;add_2 = 7;add_1 = 4294967287
add_3 = 1;add_2 = 2;add_1 = 4294967295
add_3 = 7;add_2 = 8;add_1 = 9
add_3 = 9;add_2 = 2;add_1 = 9

I want to know why it is having all x on all the 3 addr before the repeat happens for 5 times giving some values.

2

In reply to sruthikrapa:

Hi sruthikrapa. Uninitialized variables that are of integer and reg type have a value of x at the start of simulation. The line

add_3 = x;add_2 = x;add_1 = x

is showing these initial values before they are randomized.