Doubt in macro definition

SystemVerilog
1

I am using following macro definition.

`define CHECK1 (no1, no2)
par1 = no1;
par2 = no2;

I use that macro in my code as below
begin
`CHECK1 (5, 10)
end

Following error occurs
ncv_log *E NOTSTT Expecting a statement [9(IEEE)]

I dont find anything wrong in this code. Can anyone tell me where may be the error?

2

Is it like, macros can not be used/called in a function?

3

In reply to Sivapriya:

Sivapriya,
No such restriction per-se. Your code has a small syntax error - the macro definition can’t have a space before the argument list.

i.e. Replace

`define CHECK1 (no1, no2)\
par1 = no1; \
par2 = no2;

with:


`define CHECK1(no1, no2)\
par1 = no1; \
par2 = no2;

A space indeed matters here…Soon you can see a blog on this topic @ our blog - Verification Course Blog | VeriLog Courses | CVC

Regards
Ajeetha, CVC