Don't care option in case with enums

SystemVerilog
1

I have a enum of 4 bits I try to use in case when number of cases are don’t care .
Below the code snippet , I’ve tried multiple choices for ignore , but with no avail , once one of the states is STATE0 it doesn’t catch the first option

1.  {STATE0,'x},{'x,STATE0} :  begin 
2.  {STATE0,'z},{'z,STATE0} :  begin

///////////////////////////////////////////////////////////////////////////////////////////////////

 case ({current_state[0], current_state[1]})
                   {STATE0,4'b????},{4'b????,STATE0} :  begin 
                                       prev_state = current_state ;
                                       current_state = STATE0;
                                        end 
                   {STATE1,STATE2},{STATE2,STATE1} : begin 
                                       prev_state = current_state ;
                                       current_state = STATE1;
                                      end 
                 endcase 
             end
2

Look at using the case inside construct.

or use casez